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E2C0020-29-53
Semiconductor MSC1209
Semiconductor
This version: May 1999 MSC1209 Previous version: Nov. 1997
42-Bit Vacuum Fluorescent Display Tube Driver with Digital Dimming Function
GENERAL DESCRIPTION
The MSC1209 is a Bi-CMOS display driver for a 1/2-duty vacuum fluorescent display tube. The MSC1209 consists of an 84-bit shift register, an 84-bit latch circuit, a 10-bit digital dimming circuit, 42-bit segment drivers, a 2-bit grid circuit, and a cascade control circuit. The MSC1209 is interfaced with a microcontroller by using three signal lines of LOAD, CLOCK, and DATA. The cascaded MSC1209 ICs can share LOAD, CLOCK, and DATA.
FEATURES
* Power supply voltage: 8V to 18V (Built-in 5V regulator for logic) * Operating temperature range: -40 to +105C * Driving 42 segments directly: VOH=VDD-0.5V at IOH=-3.0mA (VDD=15.0V) * Built-in digital dimming circuit 10-bit resolution Programmable in the duty range of 0/2048 (0%) to 1016.5/2048 (49.6%) * 3 interfaces with microcontroller: LOAD, CLOCK, DATA * Cascade connection available (The cascaded MSC1209 ICs can share LOAD, CLOCK, and DATA.) * Built-in oscillation circuit with an external capacitor (a single pin is used) * Built-in power-on reset circuit * Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSC1209GS-2K)
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Semiconductor
MSC1209
BLOCK DIAGRAM
GRID1
GRID2
SEG1
SEG42
2-bit Grid Driver VDD VSS Voltage Regulator 5V 5V POR
42-bit Segment Driver
VDD=8 to 18V Level Shifter VCC=5.0V (Regulator)
BLANK MODEA
Timing Generator
Multiplexer
POR OSC OSC 10-bit Digital Dimming POR L 10-bit Latch 84 bits MODEB LOAD LOAD Timing Control 10-bits (Q1 to Q10) POR DATA CLOCK D 2-bit S/R D Q1-Q84 84-bit Shift Register 84-bit Latch SEL
L
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Semiconductor
MSC1209
INPUT AND OUTPUT CONFIGURATION
* Schematic Diagram of Logic Portion Input * Schematic Diagram of Logic Portion Input Circuit 1 Circuit 2
VDD (5V Reg.) VDD (5V Reg.)
INPUT
SEL
VSS
VSS
VSS
VSS
* Schematic Diagram of Logic Portion Output * Schematic Diagram of Driver Output Circuit Circuit
(5V Reg.)
VDD
OUTPUT
OUTPUT
VSS
VSS
VSS
VSS
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
1 2 3 4 5 6 7 8 9 10 11 12 13 14
,
MSC1209
56 55 54 53 52 51 50 49 48 47 46 45 44 43
SEG 3 SEG 2 SEG 1 SEL MODEB LOAD CLOCK NC DATA VSS MODEA OSC BLANK GRID2
42 41 40 39 38 37 36 35 34 33 32 31 30 29
GRID1 VDD SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31
SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 NC SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 NC: No connection 56-Pin Plastic QFP
15 16 17 18 19 20 21 22 23 24 25 26 27 28
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Semiconductor
MSC1209
PIN DESCRIPTION
Pin 48 50 Symbol DATA CLOCK Type Connected to I I Microcontroller Microcontroller Description Serial data input. (Positive logic) Receives display data and dimming data. Shift clock input. Serial data is shifted on the rising edge of this shift clock pulse. Load pulse input. The load signal is input when the transfer of serial data is completed. Segment driver output. Grid driver output. When this pin is set to "L", the display goes on. Connect an external PNP transistor to this pin. The segment data of the first bit (S1) to the 42nd bit (S42) is valid in the 84-bit segment data. Grid driver output. When this pin is set to "L", the display goes on. Connect an external PNP transistor to this pin. The segment data of the 43rd bit (S43) to the 84th bit (S84) is valid in the 84-bit segment data. Input with pull-up resistor for display blank. When this pin is set to "L", the display goes off. (SEGn="L") Input and output for oscillation. Connect an external capacitor of 68pF. 45 68pF The typical value of oscillating frequency is 512kHz. These pins specify the operating mode. 46 MODEA I 52 MODEB -- MODEA 0 1 0 1 MODEB 0 0 1 1 Operating Mode Master Operation Test Mode Slave Operation Slave Operation
51
LOAD
I
Microcontroller
1 to 20, 22 to 40, SEG1 to SEG42 54 to 56 42 GRID1
O
Anode electrode of VFD tube Grid electrode of VFD tube
O
43
GRID2
O
Grid electrode of VFD tube --
44
BLANK
I
45
OSC
I/O
--
53 41 47
SEL VDD VSS
O -- --
MODEA pin at slave side Power source Power source
SEL pin of the master IC outputs switching signals for the segment data that corresponds to the grid signals. The SEL pin of the master IC is connected to the MODEA pin of the slave IC. Power supply pin (8V to 18V). GND pin. (Ground)
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Semiconductor
MSC1209
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VIN PD TSTG Condition -- All input pins Ta25C -- Rating -0.3 to +20 -0.3 to +6.0 257 -65 to +150 Unit V V mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage "H" Input Voltage "L" Input Voltage "H" Driver Output Current CLOCK Frequency Oscillation Frequency Grid Frequency Operating Temperature Symbol VDD VIH VIL IO-1 IO-2 fC fOSC fGRID TOP Condition -- All input pins other than OSC All input pins other than OSC VDD=10.8V, 1 driver at the ON state VDD=10.8V, all drivers at the ON state -- C=68pF C=68pF -- Min. 8.0 3.8 -0.3 -- -- -- 307.2 150 -40 Typ. -- -- -- -- -- -- 512 250 -- Max. 18.0 5.5 +0.8 -2.2 -92.4 1.0 716.8 350 +105 Unit V V V mA mA MHz kHz Hz C
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Semiconductor
MSC1209
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage "L" Input Voltage "H" Input Current Symbol VIH VIL IIH1 IIH2 "L" Input Current IIL1 IIL2 "H" Output Voltage VOH1 VOH2 VOH3 VOH4 VOH5 "L" Output Voltage VOL1 VOL2 VOL3 VOL4 VOL5 VOL6 Supply Current IDD Unless otherwise specified: Ta=-40 to +105C, VDD=8.0 to 18.0V Condition Min. Max. Unit Applied pin -- -- VDD=18.0V, VIH1=5.0V VDD=18.0V, VIH2=5.0V VDD=18.0V, VIL1=0.0V VDD=18.0V, VIL2=0.0V VDD=9.5V, IOH1=-2.0mA VDD=12.0V, IOH2=-2.5mA VDD=15.0V, IOH3=-3.0mA VDD=9.5V, IOH4=-0.8mA VDD=12.0V, IOH5=-1.0mA VDD=9.5V, IOL1=500mA VDD=9.5V, IOL2=200mA VDD=9.5V, IOL3=1.0mA VDD=9.5V, IOL4=500mA VDD=9.5V, IOL5=200mA VDD=12.0V, IOL6=1.0mA fOSC=512kHz, no load 3.8 -0.3 -1.0 -60 -1.0 -500 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 4.0 -- -- -- -- -- -- -- 5.5 +0.8 +1.0 +60 +1.0 -100 -- -- -- -- -- 4.0 2.0 4.0 2.0 1.0 1.0 20 V V mA mA mA mA V V V V V V V V V V V mA SEL VDD-VSS SEL SEG1 to 42 All input pins All input pins other than BLANK BLANK All input pins other than BLANK BLANK SEG1 to 42
GRID1 to 2
AC Characteristics
(Ta=-40 to +85C, VDD=8 to 18V) Parameter CLOCK Frequency CLOCK Pulse Width CLOCK Rise/Fall Time DATA Setup Time DATA Hold Time CLOCKAE LOAD Time LOADAE CLOCK Time LOAD Pulse Width SEGn Rise/Fall Time SEL Rise/Fall Time VDD-DATA Input Time at VDD ON VDD-Hold Time at VDD OFF VDD Rise Time at VDD ON Symbol fC(1/tCLOCK) tCW tCR/tCF tDS tDH tCL tLC tLW tR/tF tR/tF fPDA fPDF fPR2 Condition -- -- -- -- -- -- -- -- CL=50pF CL=50pF When mounted in a unit When mounted in a unit -- Min. -- 400 -- 200 200 100 100 1.0 -- -- 300 5.0 -- Max. 1.0 -- 300 -- -- -- -- -- 1.0 1.0 -- -- 100 Unit MHz ns ns ns ns ns ns ms ms ms ms ms ms
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Semiconductor
MSC1209
TIMING DIAGRAM
1) Data Timing
SEL
tCR tCF tCL tDS tDH tLC tLW tCLOCK tCW tCW
3.8V 0.8V 3.8V 0.8V 3.8V 0.8V
CLOCK
DATA
VALID
VALID
VALID
VALID
2) Reset Timing
VDD
tPRZ tPDA tPOF
80%VDD 0.0V 3.8V
DATA
0.8V
3) Output Timing
tR tF 0.8VDD 0.2VDD SEL t R tF 4.0V 1.0V
SEGn, GRIDn
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Semiconductor
MSC1209
FUNCTIONAL DESCRIPTION
DATA Input This device uses 10-bit dimming data (D1 to D10) and 84-bit segment data (S1 to S84). To transfer these data, the mode bits (M0 and M1) must be sent after each of these data succeedingly. The data transfer timing diagram is shown below.
D1 D2 D10 M0 M1 S1 S2 S83 S84 M0 M1
DATA CLOCK LOAD
Figure 1 Data Transfer Timing
M0 : Enable bit M0 = "0": Indicates the data from the master IC. M0 = "1": Indicates the data from the slave IC. M1 : Mode specification bit M1 = "1": Indicates that the data sent on ahead is dimming data. M1 = "0": Indicates that the data sent on ahead is segment data. D1 : LSB of dimming data S1 : data for GRID1 of SEG1 S2 : data for GRID1 of SEG2 : S42 : data for GRID1 of SEG42 S43 : data for GRID2 of SEG1 : S84 : data for GRID2 of SEG42 Notes: 1. When the number of input data bits are larger, the data bits are pushed out in the same order that they are input, and 86 bits of the data counted from the bit entered last are used as valid data. (In the case of segment data) 2. When the number of input data bits are smaller, the data remaining in the shift register before data transfer is shifted and used as valid data. CLOCK Input Data is shifted at the rising edge of the clock. LOAD Input The contents of the shift register are shifted in while the LOAD input is "H" level and latched at "H" to "L" transition. This LOAD signal is regenerated in the VFD tube driver for the latch pulse for dimming data and segment data. When 10-bit dimming data and 84-bit segment data have been transferred, input the LOAD signal prior to the next clock.
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Semiconductor Blank Function
MSC1209
Inputting a "L" level to the BLANK pin turns display off (segment output = "L"). At this time, grid outputs are output normally. Initial Setting When power is turned on (i.e., when segment data has never been transferred), the display is turned off (segment output = "L"). Display is turned on at the moment when transfer of the segment data is complete. The relationship between the data transfer and display is shown in Figure 2.
VDD DATA LOAD SEGn Display OFF Display ON Dimming Data Segment Data
Figure 2 Relationship Between Data Transfer and Display
If, after power-on, the segment data is transferred before the dimming data is transferred, display is turned on at the moment when transfer of the segment data is complete, at which time the dimming value is undefined. The relationship between the data transfer and display is shown in Figure 3.
VDD DATA LOAD SEGn Display OFF Segment Data Dimming Data
Undefined Dimming Value Display ON
Figure 3 Relationship Between Advanced Transfer of Segment Data and Display
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Semiconductor Oscillator
MSC1209
Connect an external capacitor (C), as shown in Figure 4. The oscillating frequency fOSC depends on the external capacitor used. The following equation is true between fOSC and grid frequency (fGRID): fGRID = fOSC/2048
OSC Pin fOSC C (68pF)
Figure 4 Oscillator Equivalent Circuit
Dimming Function The duty cycle of grid output can be changed in 1/2048 step with respect to 10-bit dimming data. Table 1 shows the relationship between dimming data and duty ratio. Table 1 Dimming Data and Duty Ratio
(MSB) 00 00 Dimming Data 0000 0000 (LSB) 0000 0001 0111 1000 1001 1110 Duty Ratio 0/2048 1/2048 1015/2048 1016/2048 1016.5/2048 1016.5/2048
~
~
11 11 11
1111 1111 1111
~
~
11
1111
Max O Max
~
~
Note: Setting for address 3FFH is invalid. Duty ratios are programmable within the range of 0/2048 (0%) to 1016.5/2048 (49.6%). Figure 5 shows the grid output timing. Cascade Connection When two MSC1209 ICs are used in cascade connection, use the MODEA and MODEB pins to connect them, as shown below.
MSC1209 (Master) MODEA MODEB OSC SEL 5V MSC1209 (Slave) MODEA MODEB OSC SEL OPEN
~
~
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Semiconductor
MSC1209
The IC where the MODEA and MODEB pins are set to "L" operates as the master, and the one where the MODEB pin is set to "H" as the slave. By connecting the master side SEL output pin to the slave side MODEA pin, the segments on the slave side operate in synchronization with the grid on the master side.
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Semiconductor GRID Output Timing
tFOSC (fOSC) SEGn SEL * Dimming Data; 3FE[H] to 3F9[H] GRID1 GRID2 Display ON Display OFF Display ON Display OFF Display OFF Display ON S43 - S84
tBLANK1 tBLANK2
MSC1209
tGRID
S1 - S42
S43 - S84
* Dimming Data; 3F8[H] GRID1 GRID2 Display ON Display OFF Display ON Display OFF Display OFF Display ON
* Dimming Data; 002[H] GRID1 GRID2 ON Display OFF ON Display OFF Display OFF ON
* Dimming Data; 001[H] GRID1 GRID2 ON Display OFF ON Display OFF Display OFF ON
* Dimming Data; 000[H] GRID1 GRID2 Display OFF Display OFF
tFOSC = 2ms Typical tGRID = 2048tFOSC tBLANK1 = 2tFOSC, tBLANK2 = 5.5tFOSC Figure 5 Dimming Data and Duty Ratio
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Semiconductor
MSC1209
APPLICATION CIRCUIT
* When one MSC1209 IC is used
(SEG1 to 42) 1
SEG1 LOAD CLOCK DATA MODEA MODEB OSC VSS
SEG42 GRID1 GRID2 SEL
CPU
VF Display Tube
VDD
* When two MSC1209 ICs are used
(SEG1 to 42) 2
SEG1 LOAD CLOCK DATA MODEA MODEB OSC VSS
SEG42 GRID1 GRID2 SEL 5V VDD
SEG1 LOAD CLOCK DATA MODEA MODEB OSC VSS
SEG42 GRID1 GRID2
CPU
VF Display Tube
VDD
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Semiconductor
MSC1209
PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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E2Y0002-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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